Associate Provost (Digital Learning)
Professor, Department of Electrical Engineering
Chair, IEEE Hong Kong Section
City University of Hong Kong
Modeling and Exploration of RISC-V Architecture with High Level Synthesis
Efficient design space exploration (DSE) of RISC-V architectures is a critical and challenging task, particularly in the domain of electrical, computer, and communication engineering, where optimizing performance, power, and area (PPA) is paramount. By coupling high-level modeling and synthesis, significant improvements in design quality and productivity can be achieved. High-Level Synthesis (HLS) enables the extraction of PPA information from higher levels of abstraction, streamlining architectural DSE and facilitating innovative design strategies for dense-control applications such as RISC-V processors.
In this presentation, we propose ASLP, a novel technique to enhance HLS for synthesizing dense-control designs, achieving dynamic loop pipelining — a feature typically reserved for manual processor design workflows. This advancement paves the way for HLS-based modeling of RISC-V architectures, offering a foundation for PPA-constrained DSE frameworks. By integrating ASLP into the HLS flow, we demonstrate how these techniques can streamline processor design while maintaining high efficiency and scalability. Future work, such as incorporating machine learning into this framework, promises to further accelerate exploration and enhance outcomes.
Prof. Ray C.C. Cheung is currently the Associate Provost at City University of Hong Kong, and Professor in the Department of Electrical Engineering. He received the BEng and MPhil degrees in computer engineering and computer science and engineering at CUHK, and the PhD degree and DIC in computing at Imperial College London, United Kingdom. He was with Stanford University and UCLA as a visiting scholar. He received the Hong Kong Croucher Foundation Fellowship for his postdoctoral study at UCLA and worked as a visiting research fellow at Princeton University.
His research team, CityU Architecture Lab for Arithmetic and Security (CALAS), focuses on secure processor design, reconfigurable trusted computing, AIoT, applied cryptography, and high-performance VLSI designs. He also co-founded the Xilinx Research Lab at CityU. He is the founding technical chair of IEEE FPT Hong Kong (2002), general chair of ARC 2012, and general co-chair of FPT 2022. He is a Senior Member of IEEE, IEEE HK Section Chair 2024, and author/co-author of more than 250 international journal and conference papers. He is the chairman of Hong Kong STEM Education Alliance and founder of Hour of Code Hong Kong.